1. Field of the Invention
This invention relates to integrated circuit fabrication and more particularly to an MOS isolation process which avoids local oxidation in field regions and the problems associated therewith.
2. Description of the Relevant Art
It is generally well known that MOS integrated circuits are self-isolated, provided the source-substrate and drain-substrate pn junctions are held at reverse bias. If the pn junctions are forward biased, a drain current will flow from the source to the drain through a channel under the gate. The self-isolation property of MOS devices represents a substantial area savings for integrated circuit devices using such technology. Hence, densely patterned integrated circuits are generally fabricated with MOS technology.
Forming an integrated circuit involves interconnecting sets of integrated circuit devices which can be activated according to a specific circuit function. Thus, integrated circuit devices are typically referred to as "active devices" and a complex integrated circuit can embody several hundred thousand or more active devices on a single monolithic substrate. The interconnect structure includes patterned conductive strips which extend across a dielectric, and the dielectric functions to electrically separate those strips from the underlying region between active devices. The region between active devices (i.e., circuit elements such as transistors, capacitors, diodes, resistors, etc.) is often termed "field region", and the dielectric which separates the field region from the overlying conductive lines is generally termed "field dielectric".
For proper isolation and functionality, the conductive strips, when active, should be prevented from forming channels in the field regions. The threshold value in the field region must therefore be quite large and, in most instances, several volts above the operation voltage of the active devices. If threshold in the field region is too low, then a field region inversion will occur causing a parasitic MOS transistor to occur.
Typically, field region threshold can be increased by either increasing the field dielectric thickness and/or raising the doping level of the underlying field region. Increasing field dielectric thickness would raise the threshold voltage, but would also give rise to step coverage problems of the conductive strips extending over the step between the field dielectric and the active diffusion areas. Increasing field dielectric is thereby moderately done in conjunction with implanting a "channel-stop implant" into the field region underneath the field dielectric.
A conventional technique used to minimize step coverage problems while ensuring accurate placement of channel-stop implant is to locally oxidize silicon in the field regions. Local oxidation is a mainstay in MOS fabrication and is generally referred to as the "LOCOS" technique. LOCOS process begins by covering the pad oxide overlying the active regions with a thin layer of silicon nitride that prevents oxidation from occurring beneath the nitride. After the nitride layer has been etched away in the field regions and prior to field dielectric growth, the silicon in the exposed regions can then be selectively implanted with the channel-stop dopant. Thus, the channel-stop implant is accurately placed since it is self-aligned to the field region opening. After the field region is implanted, a field dielectric is formed upon and/or within the field region. The field dielectric is grown in all directions causing a sloped "bird's beak" in the step locations. Bird's beak minimizes step coverage problems but, as will be explained below, causes many other problems which must be avoided in high density VLSI designs.
LOCOS process can be carried out using many different process flows, including the well known semi- or fully-recessed techniques. Regardless of the technique used, the basic LOCOS process flow remains the same. A pad oxide is blanket grown upon a silicon surface and then a nitride layer is deposited over the pad oxide. The pad oxide and nitride layers are then selectively removed to expose field regions of silicon substrate. A channel-stop dopant is then implanted and a field dielectric is thereafter grown in the exposed field regions. The pad oxide must be thick enough to minimize intrinsic stress created at the edge of the nitride film, yet must be thin enough to minimize lateral growth into the pad region and the underlying active devices. In many instances, a pad oxide of 200 to 600 angstroms is optimally needed to achieved both desired results. Even with a 200 angstrom pad oxide, lateral oxidation, often termed "encroachment" occurs whereby the growing field oxide encroaches into active regions which contain one or more active devices. Active regions are defined as those regions which exist within the semiconductor substrate between field regions.
As the field dielectric is thermally grown, the encroachment resulting therefrom appears as a bird's beak which extends into the active regions as a proportion of the field dielectric thickness. In most MOS applications, a conventional field dielectric is an oxide (or silicon dioxide), and the field dielectric is generally referred to as field oxide usually grown from a wet oxidation process, at a temperature of approximately 1000.degree. C. for three to four hours to produce a thickness of 6000 Angstroms to 10000 Angstroms. Using the above example, bird's beak encroachment is typically 0.35 .mu.m to 0.5 .mu.m per side. Such an encroachment would make a lithographically defined 1.0 .mu.m feature almost entirely disappear on the circuit following the field oxidation step. For high density MOS devices, (i.e., devices with less than 1.0 .mu.m critical dimension) LOCOS cannot be used.
Beyond encroachment, LOCOS exhibits many other problems. For example, channel-stop species such as boron rapidly segregate not only along the substrate surface but perpendicular to the surface as well. In the latter instance, perpendicular segregation into the growing field oxide causes a phenomenon known as "oxidation-enhanced diffusion" or OED. In order to minimize OED, light ion channel-stop species such as boron must be implanted sufficiently deep so that they are not absorbed by growing field oxide. However, deep or heavy doping will cause high source/drain-to-substrate capacitances and will reduce source/drain-to-substrate pn junction breakdown voltages.
Another problem inherent in LOCOS is the formation of "Kooi ribbons" which form about the active region during the field oxidation process. Specifically Kooi ribbons of silicon nitride often form on the silicon surface of the active region near the field region boundary as a result of the reaction of NH.sub.3 and silicon at that interface. The NH.sub.3 is generated from the reaction of H.sub.2 O and the masking nitride during the field oxidation step. The NH.sub.3 then diffuses through the pad oxide and reacts with the silicon substrate to form silicon nitride, Kooi ribbons. Any gate oxide formed in the active area upon the ribbon locations are thinner and of lower quality than in other areas, causing low voltage breakdown of the gate oxide. Typically, a sacrificial gate oxide must be formed and thereafter striped to remove the Kooi ribbon, causing added processing steps and burdens.
The above problems associated with LOCOS generally stem from the step used in locally growing the field oxide. For example, encroachment is a result of lateral growth from field to active regions, OED is a result of perpendicular out-diffusion from channel-stop implant to overlying, growing field oxide, and Kooi ribbons are a result of NH.sub.3 diffusion from nitride-covered active regions through the pad oxide and into the active region during field oxide growth. It would therefore be desirable to produce a fabrication process, wherein encroachment can at least be minimized and, in the optimum, eliminated altogether. Elimination of encroachment will allow the formation of devices having critical dimensions less than, for example, 1.0 .mu.m. The engineer can thereby design high density features upon the masks at critical dimensions without fear of oxide encroachment or the possibility that the on-wafer critical dimension is eliminated. It would further be desirable to produce a channel-stop implant methodology which is less susceptible to segregation and OED. The improved implant step would be carried out without having to implant the peak concentration densities at prohibitive depths. Moreover, the implant step might be carried out after high temperature cycles resulting from oxide growth are complete such that temperature-induced segregation is minimized. The oxidation step might still further be carried out without having to grow a sacrificial gate oxide necessary to remove, for example, a Kooi ribbon. The preferred, improved methodology would thereby prevent formation of a Kooi ribbon and the resulting lower quality oxide, or localized oxide thinning.